1. Field of the Invention
The present invention relates to a method of filling a recess so that it is flat with a material by a bias ECR-CVD process (electron cyclotron resonance chemical vapor deposition process), capable of uniformly filling a recess formed in a ground layer with the material. The bias ECR-CVD process is effectively applicable to the manufacture of semiconductor devices and electronic parts, in which recesses need to be filled so they are flat and uniformly with a material to form electric circuits.
2. Description of Related Art
The progressive miniaturization of electronic parts requires further improved techniques for filling up recesses formed in a ground layer, such as a substrate, with a material so that the material is deposited in the recess in a flat layer. For example, the miniaturization of semiconductor integrated circuits and the increase of the degree of integration require advanced element isolating techniques instead of the conventional LOCOS (local oxidation system) and improved LOCOS. A shallow trench isolation method is one of the advanced element isolating techniques which have been developed to cope with the miniaturization of semiconductor integrated circuits and the increase of the degree of integration. The shallow trench isolation method forms trenches (grooves) having a depth in the range of 0.3 to 1.0 .mu.m, preferably, in the range of 0.1 to 1.0 .mu.m, and a large aspect ratio in a substrate, such as a silicon substrate, by a dry etching process, and then the trenches are filed with an insulating material, such as SiO.sub.2, to form element isolating regions. Since the trench isolation method is used to fill up minute trenches having a large aspect ratio with the insulating material, it has been desired to develop techniques capable of carrying out the trench isolation method satisfactorily with high reliability.
A bias ECR-CVD process having high ability to fill up recesses with a material is effective for filling up such trenches with an insulating material to form a flat layer in the recesses on the substrate. The applicant of the present patent application has made careful studies to develop techniques relating to the bias ECR-CVD process. As is generally known, in the bias ECR-CVD process etching and deposition are simultaneously performed, which is effective for forming a flat layer by filling up recesses with a material.
However, the simple application of the bias ECR-CVD process to filling up a recess with a material has the following problems.
As shown in FIGS. 6A and 6B, the aspect ratio of a recess increases gradually with the progress of the deposition process if a deposition rate at which the material is deposited on the side surfaces of the recess (hereinafter referred to as "vertical deposition rate") and the deposition rate at which the material is deposited on the bottom surface of the recess (hereinafter referred to as "horizontal deposition rate") are equal.
FIG. 6A shows a mode of deposition of a material in filling up recesses 10a and 10b respectively having aspect ratios of 2.9 and 1/8 with the material, in which numerals 1 to 9 are ordinal numbers indicating layers deposited sequentially with the progress of the bias ECR-CVD process. In the mode of deposition of the material by the bias ECR-CVD process illustrated in FIG. 6A, it is assumed that the vertical and horizontal deposition rates respectively for the side surface and the bottom surface are equal, and that face angles that makes the etching rate and the deposition rate equal to each other are 40.degree. and 70.degree.. As is obvious from the sequential layers 1, 2 and 3 in the recesses 10a and 10b, the aspect ratios of the recesses 10a and 10b increase gradually with the progress of the bias ECR-CVD process if the vertical deposition rate and the horizontal deposition rate are equal. Such a mode of deposition is not a significant problem with the recess 10c (FIG. 6B) which has a comparatively small aspect ration, but is a significant problem with a recess which has a comparatively large aspect ratio. Such gradual increase in aspect ratio during the bias ECR-CVD process entails unsatisfactory deposition of the material in the recess and may possible form a void in the material which fills the recess.
Another problem is the dependence of the recess filling performance of the bias ECR-CVD process on the pattern of the ground layer. As shown in FIG. 7, the deposition rate for a wide recess 10c, namely, a recess having a large aspect ratio, is smaller than that for recesses (trenches) 10a and 10b respectively having large aspect ratios as compared with that of the recess 10c. Therefore, if the recess 10c is filled so that it is flat with SiO.sub.2, SiO.sub.2 which fills the recesses 10a and 10b protrudes from the surface of the ground layer in a thickness 1 as shown in FIG. 7 and, consequently, the wide recess 10c cannot completely be filled up with SiO.sub.2 if the trenches, namely, the recesses 10a and 10b, are filled up exactly by using a single mask. On the contrary, if the wide recess 10c is filled up properly and the recesses 10a and 10b are filled with SiO.sub.2, so that the layer of SiO.sub.2 protrudes from the surface of the ground layer with a thickness 1, the excessive portion of the SiO.sub.2 layer of the thickness 1 must be removed in the subsequent process by using another mask, which makes the process complicated and may possibly cause faulty removal of the excessive portion of the SiO.sub.2 layer due to the misalignment of the mask. This problem is discussed in detail in Japanese Patent Application No. Hei 1-277931 filed on Oct. 25th, 1989 by the applicant of the present patent application and which issued on Jun. 14, 1991 as Japanese Patent BO3-139860.